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MC14017B Decade Counter
The MC14017B is a five-stage Johnson decade counter with built-in code converter. High speed operation and spike-free outputs are obtained by use of a Johnson decade counter design. The ten decoded outputs are normally low, and go high only at their appropriate decimal time period. The output changes occur on the positive-going edge of the clock pulse. This part can be used in frequency division applications as well as decade counter or decimal decode display applications.
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16 PDIP-16 P SUFFIX CASE 648 MC14017BCP AWLYYWW 1 16 SOIC-16 D SUFFIX CASE 751B 1 16 14017B AWLYWW
* * * * * * * *
Fully Static Operation DC Clock Input Circuit Allows Slow Rise Times Carry Out Output for Cascading Divide-by-N Counting Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range Pin-for-Pin Replacement for CD4017B Triple Diode Protection on All Inputs
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C A WL, L YY, Y WW, W
SOEIAJ-16 F SUFFIX CASE 966 1
MC14017B ALYW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC14017BCP MC14017BD MC14017BDR2 MC14017BF MC14017BFEL Package PDIP-16 SOIC-16 SOIC-16 SOEIAJ-16 SOEIAJ-16 Shipping 2000/Box 48/Rail 2500/Tape & Reel See Note 1. See Note 1.
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
(c) Semiconductor Components Industries, LLC, 2000
1
August, 2000 - Rev. 4
Publication Order Number: MC14017B/D
MC14017B
PIN ASSIGNMENT
Q5 Q1 Q0 Q2 Q6 Q7 Q3 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD RESET CLOCK CE Cout Q9 Q4 Q8
FUNCTIONAL TRUTH TABLE (Positive Logic)
Clock 0 X X Clock Enable X 1 X 0 X Reset 0 0 1 0 0 0 0 Decode Output=n n n Q0 n+1 n n n+1
BLOCK DIAGRAM
CLOCK 14 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Cout VDD = PIN 16 VSS = PIN 8 3 2 4 7 10 1 5 6 9 11 12
CLOCK 13 ENABLE
X 1
X = Don't Care. If n < 5 Carry = "1", Otherwise = "0".
RESET 15
LOGIC DIAGRAM
Q5 1 Q1 2 Q7 6 7 Q3 11 Q9
14 CLOCK CLOCK ENABLE CQ C DQ RR CQ C DQ RR CQ C DQ RR CQ C DQ RR CQ C DQ RR 12 CARRY
13
RESET
15
3 Q0
5 Q6
4 Q2
9 Q3
10 Q4
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4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF:
where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.0011.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Output Voltage Vin = VDD or 0
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)
Vin = 0 or VDD
Characteristic
IT(CL) = IT(50 pF) + (CL - 50) Vfk
"1" Level
"1" Level
"0" Level
Source
Sink
Symbol
VOH
VOL
IOH
VIH
IDD
Cin
IOL
VIL
Iin
IT
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
--
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- 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- --
MC14017B
- 55_C
3 0.1 0.05 0.05 0.05 Max 5.0 10 20 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min IT = (0.27 A/kHz) f + IDD IT = (0.55 A/kHz) f + IDD IT = (0.83 A/kHz) f + IDD 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 0.00001 Typ (4.) - 4.2 - 0.88 - 2.25 - 8.8 25_C 0.005 0.010 0.015 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.5 3.0 4.0 - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 0.05 MaxIII Unit 150 300 600 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc Adc Adc Adc Vdc Vdc Vdc Vdc pF
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I III I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I I I I IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
7. The formulas given are for the typical characteristics only at 25_C. 8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Clock Enable Removal Time
Clock Enable Setup Time
Clock Input Rise and Fall Time
Reset Removal Time
Reset Pulse Width
Clock Frequency
Clock Pulse Width
Turn-Off Delay Time Reset to Cout tPLH = (1.7 ns/pF) CL + 315 ns tPLH = (0.66 ns/pF) CL + 142 ns tPLH = (0.5 ns/pF) CL + 100 ns
Propagation Delay Time Clock to Decode Output tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
Propagation Delay Time Clock to Cout tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPLH, tPHL = (0.66 ns/pF) CL + 142 ns tPLH, tPHL = (0.5 ns/pF) CL + 100 ns
Propagation Delay Time Reset to Decode Output tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/PF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Characteristic
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Symbol
MC14017B
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tTLH, tTHL
tTLH, tTHL
tw(H)
tw(H)
tPLH
trem
trem
tsu
fcl
4 VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min 420 200 140 350 150 115 750 275 210 500 250 190 250 100 75 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- No Limit Typ (8.) 260 100 70 175 75 52 375 135 105 250 125 95 125 50 35 400 175 125 500 230 175 400 175 125 500 230 175 100 50 40 5.0 12 16 1000 460 350 1000 460 350 Max 800 350 250 800 350 250 200 100 80 2.0 5.0 6.7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MHz Unit ns ns ns ns ns ns ns ns ns ns --
MC14017B
VDD Vout Output Sink Drive Decode Outputs ID Carry VGS = VDS = Output Source Drive Clock to desired outputs (S1 to B) S1 to A - VDD Vout - VDD
VSS
VDD VSS
A B
S1 S1
CLOCK Q0 ENABLE Q1 Q2 Q3 Q4 RESET Q5 Q6 Q7 Q8 Q9 CLOCK Cout VSS
(S1 to A)
Clock to 5 thru 9 (S1 to B) VDD Vout
EXTERNAL POWER SUPPLY
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD 500 F ID 0.01 F CERAMIC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Cout VSS CL CL CL CL CL CL CL CL CL CL CL
CLOCK ENABLE RESET PULSE GENERATOR fc
CLOCK
Figure 2. Typical Power Dissipation Test Circuit
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5
MC14017B
APPLICATIONS INFORMATION Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
RESET CLOCK CE MC14017B
Q0 Q1 * * * Q8 Q9
RESET CLOCK CE MC14017B
Q0Q1 * * * Q8 Q9
RESET CLOCK CE MC14017B
Q1 * * * Q8 Q9 8 DECODED OUTPUTS
9 DECODED OUTPUTS CLOCK
8 DECODED OUTPUTS
FIRST STAGE
INTERMEDIATE STAGES
LAST STAGE
Figure 3. Counter Expansion
Pcp CLOCK CLOCK ENABLE trem RESET 20 ns Q0 tPLH Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Cout tPLH tPLH
Ncp trem 20 ns tPHL tPHL tPHL tPHL 50% tPLH tPLH tPLH tTHL 10% tPLH tTHL tPHL tPHL tPHL 90% tTHL tPHL tTLH tTLH tTHL tTHL tsu 20 ns tPLH 20 ns 20 ns
90% 10%
50%
VDD VSS VDD VSS VDD VSS
20 ns tPLH tTLH 90% 10% tTLH tTLH 50% tTHL tTHL
VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL
tPHL tTHL
tTLH
tPLH tTLH tTHL tPLH tTLH tPLH tPHL tTHL tPHL tTHL
tPHL
tTLH
Figure 4. AC Measurement Definition and Functional Waveforms
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MC14017B
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
-A-
16 9
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC14017B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
16 9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local Sales Representative.
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MC14017B/D

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